MMU implementation

Short question: where does page table reside? Is it in MMU (totally hardware implementation) or in RAM (OS involved)?

I am trying to figure out whether the RAM access involved in mapping linear address onto physical in case of TLB miss. I guess the answer in "no" and implementation is totally hardware, but I am not sure. I saw mention that it can be as hardware as software, but I am interested in common case of Intel processors.

Answers


TLB in Intel architecture is handled in the hardware. This paper from intel references the TLB implementation.


Need Your Help

Restore sharepoint 2010 web application on different domain

deployment sharepoint-2010 backup

We made a backup of a web application through the central administration to move it to a different server on a different domain and it's a domain controller actually.

DirectX-11 Vertex Shader Runtime Compilation Issue

visual-studio directx shader directx-11 direct3d11

I'm trying to follow this simple Direct3D tutorial by Microsoft online here: http://msdn.microsoft.com/en-us/library/windows/apps/ff729719.aspx.