Short question: where does page table reside? Is it in MMU (totally hardware implementation) or in RAM (OS involved)?
I am trying to figure out whether the RAM access involved in mapping linear address onto physical in case of TLB miss. I guess the answer in "no" and implementation is totally hardware, but I am not sure. I saw mention that it can be as hardware as software, but I am interested in common case of Intel processors.
TLB in Intel architecture is handled in the hardware. This paper from intel references the TLB implementation.